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Triple-Channel Digital Isolator with Programmable Default Output ADuM1310
FEATURES
Pb-free, 16-lead, wide body SOIC package Low power operation 5 V operation 1.0 mA per channel max @ 0 Mbps to 2 Mbps 3.5 mA per channel max @ 10 Mbps 3 V operation 0.7 mA per channel max @ 0 Mbps to 2 Mbps 2.1 mA per channel max @ 10 Mbps 3 V/5 V level translation High temperature operation: 105C Up to 10 Mbps data rate (NRZ) Programmable default output state Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE certificate of conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 560 V peak
GENERAL DESCRIPTION
The ADuM13101 is a unidirectional, triple-channel digital isolator based on Analog Devices, Inc. iCoupler(R) technology. Combining high speed CMOS and monolithic coreless transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects, are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discretes is eliminated with these iCoupler products. Furthermore, iCoupler devices run at one-tenth to one-sixth the power consumption of optocouplers at comparable signal data rates. The ADuM1310 isolator provides three independent isolation channels at data rates up to 10 Mbps. It operates with the supply voltage of either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. This product also has a default output control pin. This allows the user to define the logic state the outputs are to adopt in the absence of the input VDD1 power. Unlike other optocoupler alternatives, the ADuM1310 has a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.
ADuM1310
VDD1 1 GND1 2 VIA 3 VIB 4 VIC 5 NC 6 DISABLE 7 GND1 8 NC = NO CONNECT ENCODE ENCODE ENCODE DECODE DECODE DECODE
16
APPLICATIONS
General-purpose, unidirectional, multichannel isolation
FUNCTIONAL BLOCK DIAGRAM
VDD2 GND2 VOA VOB VOC NC CTRL GND2
15
14
13
12
11
10
Figure 1.
1
Protected by U.S. Patents 5,952,849; 6,873,065; and other pending patents.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
04904-001
9
ADuM1310 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics--5 V Operation................................ 3 Electrical Characteristics--3 V Operation................................ 4 Electrical Characteristics--Mixed 5 V/3 V or 3 V/5 V Operation....................................................................................... 5 Package Characteristics ............................................................... 7 Insulation and Safety-Related Specifications............................ 7 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics .............................................................................. 8 Recommended Operating Conditions ...................................... 8 Absolute Maximum Ratings ............................................................9 Regulatory Information................................................................9 ESD Caution...................................................................................9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Application Information................................................................ 12 PC Board Layout ........................................................................ 12 Propagation Delay-Related Parameters................................... 12 DC Correctness and Magnetic Field Immunity........................... 12 Power Consumption .................................................................. 13 Power-Up/Power-Down Considerations ................................ 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
10/06--Rev. D to Rev. E Removed ADuM1410 ........................................................Universal Updated Format..................................................................Universal Change to Figure 3 ......................................................................... 10 Changes to Table 10........................................................................ 10 Changes to Application Information ........................................... 12 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 3/06--Rev. C to Rev. D Added Note 1 and Changes to Figure 2......................................... 1 Changes to Absolute Maximum Ratings ..................................... 11 11/05--Rev. SpB to Rev. C 5/05--Rev. SpA to Rev. SpB Changes to Table 6.............................................................................9 10/04--Data Sheet Changed from Rev. Sp0 to Rev. SpA Changes to Table 5.............................................................................9 6/04--Revision Sp0: Initial Version
Rev. E | Page 2 of 16
ADuM1310 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--5 V OPERATION
4.5 V VDD1 5.5 V, 4.5 V VDD2 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V; all voltages are relative to their respective ground. Table 1.
Parameter DC SPECIFICATIONS Total Supply Current, Three Channels 1 VDD1 Supply Current, Quiescent VDD2 Supply Current, Quiescent VDD1 Supply Current, 10 Mbps Data Rate VDD2 Supply Current, 10 Mbps Data Rate Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Enable Time 8 Input Disable Time8 Input Dynamic Supply Current per Channel 9 Output Dynamic Supply Current per Channel9
1
Symbol
Min
Typ
Max Unit
Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IIA, IIB, IIC, -10 IID, ICTRL, IDISABLE VIH VIL 0.8 VOAH, VOBH, VDD1, VDD2 - 0.4 VOCH, VODH VOAL, VOBL, VOCL, VODL PW tPHL, tPLH PWD tPSK tPSKCD tR/tF |CMH| |CML| fr tENABLE tDISABLE IDDI (D) IDDO (D) 10 20
2.4 1.2 6.6 2.1 +0.01
3.2 1.6 9.0 3.0 +10 2.0
mA mA mA mA A V V V V
VIA = VIB = VIC = VID = 0 VIA = VIB = VIC = VID = 0 5 MHz logic signal frequency 5 MHz logic signal frequency 0 VIA, VIB, VIC, VID, VDISABLE VDD1, 0 VCTRL VDD2
4.8 0.2 0.4
IOx = -4 mA, VIx = VIxH IOx = +4 mA, VIx = VIxL
100 30 5 30 5 25 25 2.5 35 35 1.2 2.0 5.0 0.19 0.05 50 5
ns Mbps ns ns ps/C ns ns ns kV/s kV/s
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Mbps s VIA, VIB, VIC, VID = 0 or VDD1 s VIA, VIB, VIC, VID = 0 or VDD1 mA/Mbps mA/Mbps
Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total IDD1 and IDD2 supply currents as a function of the data rate for the ADuM1310 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (see Table 9). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. E | Page 3 of 16
ADuM1310
ELECTRICAL CHARACTERISTICS--3 V OPERATION
2.7 V VDD1 3.6 V, 2.7 V VDD2 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C, VDD1 = VDD2 = 3.0 V; all voltages are relative to their respective ground. Table 2.
Parameter DC SPECIFICATIONS ADuM1310, Total Supply Current, Three Channels 1 VDD1 Supply Current, Quiescent VDD2 Supply Current, Quiescent VDD1 Supply Current, 10 Mbps Data Rate VDD2 Supply Current, 10 Mbps Data Rate Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew (Equal Temperature) 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Enable Time 8 Input Disable Time8 Input Dynamic Supply Current per Channel 9 Output Dynamic Supply Current per Channel9
1
Symbol
Min
Typ
Max Unit
Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IIA, IIB, IIC, IID, -10 ICTRL, IDISABLE VIH VIL 0.4 VOAH, VOBH, VDD1, VDD2 - 0.4 VOCH, VODH VOAL, VOBL, VOCL, VODL PW tPHL, tPLH PWD tPSK tPSKCD tR/tF |CMH| |CML| fr tENABLE tDISABLE IDDI (D) IDDO (D) 10 20
1.2 0.8 3.4 1.1 +0.01
1.6 1.0 4.9 1.3 +10 1.6
mA mA mA mA A V V V V
VIA = VIB = VIC = VID = 0 VIA = VIB = VIC = VID = 0 5 MHz logic signal frequency 5 MHz logic signal frequency 0 VIA, VIB, VIC, VID, VDISABLE VDD1, 0 VCTRL VDD2
2.8 0.2 0.4
IOx = -4 mA, VIx = VIxH IOx = +4 mA, VIx = VIxL
100 30 5 30 5 25 25 2.5 35 35 1.1 2.0 5.0 0.10 0.03 50 5
ns Mbps ns ns ps/C ns ns ns kV/s kV/s Mbps s s mA/Mbps mA/Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V VIA, VIB, VIC, VID = 0 or VDD1 VIA, VIB, VIC, VID = 0 or VDD1
Supply current values are for all channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total IDD1 and IDD2 supply currents as a function of the data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (see Table 9). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. E | Page 4 of 16
ADuM1310
ELECTRICAL CHARACTERISTICS--MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation 1 : 4.5 V VDD1 5.5 V, 2.7 V VDD2 3.6 V; 3 V/5 V operation: 2.7 V VDD1 3.6 V, 4.5 V VDD2 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V. Table 3.
Parameter DC SPECIFICATIONS ADuM1310, Total Supply Current, Three Channels 2 VDD1 Supply Current, Quiescent 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current, Quiescent 5 V/3 V Operation 3 V/5 V Operation VDD1 Supply Current, 10 Mbps Data Rate 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current, 10 Mbps Data Rate 5 V/3 V Operation 3 V/5 V Operation Input Currents Logic High Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 3 Maximum Data Rate 4 Propagation Delay 5 Pulse Width Distortion, |tPLH - tPHL|5 Change vs. Temperature Propagation Delay Skew 6 Channel-to-Channel Matching 7 Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation Common-Mode Transient Immunity at Logic High Output 8 Common-Mode Transient Immunity at Logic Low Output8 Symbol Min Typ Max Unit Test Conditions
IDDI (Q) 2.4 1.2 IDDO (Q) 0.8 1.2 IDD1 (10) 6.5 3.4 IDD2 (10) 1.1 1.9 +0.01 1.3 2.2 +10 mA mA A 5 MHz logic signal frequency 5 MHz logic signal frequency 0 VIA, VIB, VIC, VID, VDISABLE VDD1, 0 VCTRL VDD2 8.2 4.9 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 1.0 1.6 mA mA VIA = VIB = VIC = VID = 0 VIA = VIB = VIC = VID = 0 3.2 1.6 mA mA VIA = VIB = VIC = VID = 0 VIA = VIB = VIC = VID = 0
IIA, IIB, IIC, IID, ICTRL, IDISABLE VIH
-10
2.0 1.6 VIL 0.8 0.4 VDD1/VDD2 - 0.4 VDD1/VDD2 - 0.2 0.2 0.4
V V V V V V
VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL PW tPHL, tPLH PWD tPSK tPSKCD tR/tf
IOx = -4 A, VIx = VIxH IOx = +4 A, VIx = VIxL
100 10 20 30 5 30 5 3.0 2.5 35 35 50 5
ns Mbps ns ns ps/C ns ns ns ns kV/s kV/s
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
|CMH| |CML|
25 25
Rev. E | Page 5 of 16
ADuM1310
Parameter Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Enable Time 9 Input Disable Time9 Input Dynamic Supply Current per Channel 10 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current per Channel10 5 V/3 V Operation 3 V/5 V Operation
1 2
Symbol fr
Min
Typ 1.2 1.1
Max Unit Mbps Mbps s s
Test Conditions
tENABLE tDISABLE IDDI (D) 0.19 0.10 IDDO (D) 0.03 0.05
2.0 5.0
VIA, VIB, VIC, VID = 0 or VDD1 VIA, VIB, VIC, VID = 0 or VDD1
mA/Mbps mA/Mbps
mA/Mbps mA/Mbps
All voltages are relative to their respective ground. Supply current values are for all channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total IDD1 and IDD2 supply currents as a function of the data rate. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (see Truth Table - Table 9). 10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. E | Page 6 of 16
ADuM1310
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)2 Input Capacitance 2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2
1
Symbol RI-O CI-O CI JCI JCO
Min
Typ 1012 2.2 4.0 33 28
Max
Unit pF pF C/W C/W
Test Conditions f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside
2
Device considered a 2-terminal device. Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 shorted together. Input capacitance is from any input data pin to ground.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol Value 2500 L(I01) 7.7 min L(I02) Unit Conditions V rms 1-minute duration mm Measured from input terminals to output terminals, shortest distance through air 8.1 min mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Insulation distance through insulation >175 V DIN IEC 112/VDE 0303 Part 1 IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. E | Page 7 of 16
ADuM1310
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
The ADuM1310 isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage. Category I through Category IV listed in the characteristic column are per DIN EN 60747-5-2 definition. Table 6.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge <5 pC Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge <5 pC After Input and/or Safety Test Subgroup 2/3 VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge <5 pC Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; see Figure 2) Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS, VIO = 500 V
350
Symbol
Characteristic I to IV I to III I to II 40/105/21 2 560 1050
Unit
VIORM VPR VPR
V peak V peak
896 672 4000 150 265 335 >109
V peak V peak V peak C mA mA
VTR TS IS1 IS2 RS
300
SAFETY-LIMITING CURRENT (mA)
250 SIDE #2 200
150 SIDE #1 100 50 0 0 50 100 150 CASE TEMPERATURE (C) 200
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 7.
Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times
1
Symbol TA VDD1, VDD2
04904-003
Min -40 2.7
Max +105 5.5 1.0
Unit C V ms
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.
Rev. E | Page 8 of 16
ADuM1310 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 8.
Parameter Storage Temperature Ambient Operating Temperature Supply Voltages1 Input Voltage1, 2 Output Voltage1, 2 Average Output Current per Pin3 Side 1 Side 2 Common-Mode Transients4
1 2
REGULATORY INFORMATION
In accordance with UL1577, each ADuM1310 is proof tested by applying an insulation test voltage 3000 V rms for 1 second (current leakage detection limit = 5 A). In accordance with DIN EN 60747-5-2, each ADuM1310 is proof tested by applying an insulation test voltage 1050 V peak for 1 second (partial discharge detection limit = 5 pC). The ADuM1310 is approved by the following organizations: UL: Recognized under 1577 Component Recognition Program. CSA: Approved under CSA Component Acceptance Notice #5A. VDE: Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, and DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000.
Rating -65C to +150C -40C to +105C -0.5 V to +6.5 V -0.5 V to VDDI + 0.5 V -0.5 VDDO + 0.5 V to VDDO + 0.5 V
-18 mA to +18 mA -22 mA to +22 mA -100 kV/s to +100 kV/s
All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. 3 See Figure 2 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings can cause latchup or permanent damage.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 9. Truth Table (Positive Logic)
VIX Input 1 H L X X X CTRL Input X X H or NC L H or NC VDISABLE State L or NC L or NC H H X VDD1 State1 Powered Powered X X Unpowered VDD2 State1 Powered Powered Powered Powered Powered VOX Output1 H L H L H Notes Normal operation, data is high. Normal operation, data is low. Inputs disabled. Outputs are in the default state as determined by CTRL. Inputs disabled. Outputs are in the default state as determined by CTRL. Input unpowered. Outputs are in the default state as determined by CTRL. Outputs return to input state within 1 s of VDD1 power restoration. See the Power-Up/Power-Down Considerations section for more details. Input unpowered. Outputs are in the default state as determined by CTRL. Outputs return to input state within 1 s of VDD1 power restoration. See the Power-Up/Power-Down Considerations section for more details. Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 s of VDD2 power restoration. See the Power-Up/Power-Down Considerations section for more details.
X
L
X
Unpowered Powered
L
X
X
X
Powered
Unpowered Z
1
VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D).
Rev. E | Page 9 of 16
ADuM1310 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1 GND1* 2 VIA 3 VIB 4 VIC 5 NC 6 DISABLE 7 GND1* 8 NC = NO CONNECT
04904-004
16 VDD2 15 GND2*
ADuM1310
TOP VIEW (Not to Scale)
14 VOA 13 VOB 12 VOC 11 NC 10 CTRL 9
GND2*
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 3. Pin Configuration
Table 10. ADuM1310 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VDD1 GND1 VIA VIB VIC NC DISABLE GND1 GND2 CTRL Description Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected; connecting both pins to GND1 is recommended. Logic Input A. Logic Input B. Logic Input C. No Connect. Input Disable. Disables the isolator inputs and refreshes. Outputs take on logic state determined by CTRL. Ground 1. Ground reference for Isolator Side 1. Pin 8 and Pin 2 are internally connected; connecting both pins to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected; connecting both pins to GND2 is recommended. Default Output Control. Controls the logic state the outputs take on when the input power is off. VOA, VOB, and VOC outputs are high when CTRL is high or disconnected and VDD1 is off. VOA, VOB, and VOC outputs are low when CTRL is low and VDD1 is off. When VDD1 power is on, this pin has no effect. No Connect. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected; connecting both pins to GND2 is recommended. Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
11 12 13 14 15 16
NC VOC VOB VOA GND2 VDD2
Rev. E | Page 10 of 16
ADuM1310 TYPICAL PERFORMANCE CHARACTERISTICS
2.5 7 6 2.0
CURRENT/CHANNEL (mA)
5 1.5
CURRENT (mA)
4
1.0 5V 3V 0.5
3 5V 2 3V
1
04904-006 04904-009 04904-010
0 0 2 4 6 DATA RATE (Mbps) 8 10
0 0 2 4 6 DATA RATE (Mbps) 8 10
Figure 4. Typical Supply Current per Input Channel vs. Data Rate for 5 V and 3 V Operation
0.7 0.6 2.0
CURRENT/CHANNEL (mA)
Figure 7. Typical ADuM1310 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
2.5
0.5
CURRENT (mA)
0.4 5V 0.3 3V 0.2
1.5 5V 1.0 3V
0.5 0.1
04904-007
0 0 2 4 6 DATA RATE (Mbps) 8 10
0 0 2 4 6 DATA RATE (Mbps) 8 10
Figure 5. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
1.2
Figure 8. Typical ADuM1310 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
1.0
CURRENT/CHANNEL (mA)
0.8
0.6 5V 0.4 3V
0.2
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 6. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
Rev. E | Page 11 of 16
04904-008
0
ADuM1310 APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM1310 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 9). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 F and 0.1 F. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.
VDD1 GND1 VIA VIB VIC NC DISABLE GND1 NC = NO CONNECT VDD2 GND2 VOA VOB VOC NC CTRL GND2
Propagation delay skew refers to the maximum amount the propagation delay differs among multiple ADuM1310 components operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable, and is, therefore, either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than 2 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default state (see Table 9) by the watchdog timer circuit. The magnetic field immunity of the ADuM1310 is determined by the changing magnetic field which induces a voltage in the transformer's receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The ADuM1310's 3 V operating condition is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold of about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt) rn2; n = 1, 2, ... , N
Figure 9. Recommended Printed Circuit Board Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition.
INPUT (VIx) 50%
tPLH
OUTPUT (VOx)
tPHL
04904-014
04904-013
50%
where: is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).
Figure 10. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal's timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM1310 component.
Rev. E | Page 12 of 16
ADuM1310
Given the geometry of the receiving coil in the ADuM1310 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 11.
100
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
POWER CONSUMPTION
The supply current at a given channel of the ADuM1310 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by
10
1
1
IDDI = IDDI (Q) IDDI = IDDI (D) x (2f - fr) + IDDI (Q) For each output channel, the supply current is given by IDDO = IDDO (Q)
04904-015
f 0.5fr f > 0.5fr
0.01
f 0.5fr f 0.5fr
0.001 1k
10k 1M 10M 100k MAGNETIC FIELD FREQUENCY (Hz)
100M
IDDO = (IDDO (D) + CLVDDO) x (2f - fr) + IDDO (Q) where:
Figure 11. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is approximately 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V--still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1310 transformers. Figure 12 expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM1310 is extremely immune and can be affected only by extremely large currents operated at high frequency, very close to the component. For the 1 MHz example noted, a 0.5 kA current needed to be placed 5 mm away from the ADuM1310 to affect the operation of the component.
1000
MAXIMUM ALLOWABLE CURRENT (kA)
IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (Hz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (bps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 4 and Figure 5 provide per-channel supply currents as a function of the data rate for an unloaded output condition. Figure 6 provides perchannel supply current as a function of the data rate for a 15 pF output condition. Figure 7 through Figure 8 provide total IDD1 and IDD2 supply current as a function of the data rate for the ADuM1310.
DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 12. Maximum Allowable Current for Various Current-to-ADuM1310 Spacings
Rev. E | Page 13 of 16
04904-016
0.01
ADuM1310
POWER-UP/POWER-DOWN CONSIDERATIONS
Given that the ADuM1310 has separate supplies on either side of the isolation barrier, the power-up and power-down characteristics relative to each supply voltage need to be considered individually. As shown in Table 9, when VDD1 input power is off, the ADuM1310 outputs take on a default condition as determined by the state of the CTRL pin. As the VDD1 supply is increased/decreased, the output of each channel transitions from/to the default condition to/from the state matching its respective signals (see Figure 13 and Figure 14).
OUTPUT DATA OUTPUT DATA
When VDD1 crosses the threshold for activating the refresh circuit (approximately 2 V), there can be a delay of up to 2 s before the output is updated to the correct state, depending on the timing of the next refresh pulse. When VDD1 is reduced from an on state below the 2 V threshold, there can be a delay of up to 5 s before the output takes on its default state determined by the CTRL signal. This corresponds to the duration that the watchdog timer circuit at the input is designed to wait before triggering an output default state. When the VDD2 output supply is below the level at which the ADuM1310 output transistors are biased (about 1 V), the outputs take on a high impedance state. When VDD2 is above a value of about 2 V, each channel output takes on a state matching that of its respective input. Between the values of 1 V and 2 V, the outputs are set low. This behavior is shown in Figure 15 and Figure 16.
VDD1 2V (TYP)
VDD1
CTRL = HIGH OR NC
CTRL = LOW
Figure 13. VDD1 Power-Up/Power-Down Characteristics, Input Data = High
2V (TYP)
OUTPUT DATA
04904-017
OUTPUT DATA HIGH IMPEDANCE
VDD2
04904-019 04904-020
VDD1 2V (TYP)
VDD1
HIGH IMPEDANCE
Figure 15. VDD2 Power-Up/Power-Down Characteristics, Input Data = High
CTRL = HIGH OR NC
CTRL = LOW
Figure 14. VDD1 Power-Up/Power-Down Characteristics, Input Data = Low
2V (TYP) OUTPUT DATA HIGH IMPEDANCE VDD2
04904-018
OUTPUT DATA
HIGH IMPEDANCE
Figure 16. VDD2 Power-Up/Power-Down Characteristics, Input Data = Low
Rev. E | Page 14 of 16
ADuM1310 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.50 (0.0197) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 17. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADuM1310BRWZ 1 ADUM1310BRWZ-RL1, 2
1 2
Number of Channels 3 3
Maximum Data Rate (Mbps) 10 10
Temperature Range -40C to +105C -40C to +105C
Package Description 16-Lead Wide Body SOIC_W 16-Lead Wide Body SOIC_W
060606-A
Package Option RW-16 RW-16
Z = Pb-free part. The addition of an -RL suffix designates a 13-inch (1,000 units) tape and reel option.
Rev. E | Page 15 of 16
ADuM1310 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04904-0-10/06(E)
Rev. E | Page 16 of 16

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